Dr. Ramin Rajaei

Ramin Rajaei

Ph.D.

Department of Electrical Engineering

Sharif University of Technology

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Education

2010-2015:

Ph.D.

Department of Electrical Engineering, Sharif University of Technology, Tehran, IRAN

2007-2010:

M.Sc.

Department of Electrical Engineering, Sharif University of Technology, Tehran, IRAN

2003-2007:

B.Sc.

Faculty of Engineering, Ferdowsi University of Mashhad, Mashhad, IRAN

Research Interest

Fault Tolerant System Design:

Reliability Issues in VLSI Circuits: Soft Errors, Process Variation, Aging

Reliability Modeling & Estimation: Analytical and Experimental Approaches

Fault-Tolerant Microprocessors: Architecture and System Level Approaches

Non-volatile Memory Technologies

Embedded System Design:

Dependable Embedded Systems

Low Power Embedded Systems

SoC (System on Chip) Design:

NoC (Network on Chip)

Reconfigurable Systems

ASIC/FPGA design

Publications (2009-2015)

1. R. Rajaei, B. Asgari, M. Tabandeh, M. Fazeli, Two Novel Single Event Multiple Upset tolerant SRAM cell designs for sub-Micron Technologies, TUBITAK journal, 2015.

2. R. Rajaei, M. Tabandeh, M. Fazeli, Low Cost Circuit-Level Soft Error Mitigation Techniques for Combinational Logic, Scientia Iranica, Elsevier, 2015.

3. R. Rajaei, B. Asgari, M. Tabandeh, M. Fazeli, Design of Robust SRAM Cells Against Single Event Multiple Effects for Nanometer Technologies, IEEE Transactions on Device and Materials Reliability (TDMR) 2015.

4. R. Rajaei, M. Fazeli, M. Tabandeh, Soft Error-Tolerant Design of MRAM-based Non-Volatile Latches for Sequential Logics, IEEE Transactions on Magnetics (TMAG), 2014.

5. R. Rajaei, M. Tabandeh, M. Fazeli, Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations, Journal of Circuits, Systems and Computers (JCSC), World Scientific, 2014.

6. R. Rajaei, M. Tabandeh, M. Fazeli, Soft Error Rate Estimation for Combinational Logic in Presence of Single Event Multiple Transients, Journal of Circuits, Systems and Computers (JCSC), World Scientific, 2014.

7. R. Rajaei, M. Tabandeh, M. Fazeli, Low Cost Soft Error Hardened Latch Designs for Nano-scale CMOS Technology in presence of Process Variation, Microelectronic Reliability (MR), Elsevier, 2013.

8. R. Rajaei, M. Tabandeh, B. Rashidian, Single Event Upset Immune Latch Circuit Design Using C-Element, The IEEE 9^th International Conference on ASIC (ASICON2011), 25-28 Oct, 2011, Xiamen, China.

9. R. Rajaei, M. Tabandeh, B. Rashidian, Design of a Radiation Hardened Parallel IO Port using Dual Modular Redundancy with Feedback Voting, IEEE International SOC Design Conference (ISOCC2011), 17-18 Nov., Jeju, Korea.

10. R. Rajaei, S. Hessbi, B. Vosoughi Vahdat, An Energy-Aware Methodology for Mapping and Scheduling of Concurrent Applications in MPSoCs, 19th Iranian conference on electrical engineering (ICEE 2011), Tehran, Iran, May 17-19, 2011.

11. R. Rajaei, A Survey on Mapping and Scheduling Algorithms in Network on Chips, (in Persian), 13th Iranian Student Conference on Electrical Engineering, (Graduate part), 15-17 Sep. 2010, Tarbiat Modarres University, Tehran, Iran.

12. R. Rajaei, Evaluating of the Routing Algorithms and presenting a Novel Adaptive Algorithm for Network on Chips, (in Persian), 13th Iranian Student Conference on Electrical Engineering, (Graduate part), 15-17 Sep. 2010, Tarbiat Modarres University, Tehran, Iran.

13. R. Rajaei, B. Vosoughi Vahdat, S. Hessabi, A novel energy-aware mapping algorithm for Network on Chip, (in Persian), 18^th Iranian conference on electrical engineering (ICEE 2010), Isfahan, Iran, May 11-13, 2010.

14. O. Khayat, M. M. Ebadzadeh, H. R. Shahdoosti, R. Rajaei, I. Khajehnasiri, A novel hybrid algorithm for creating self-organizing fuzzy neural networks, Neurocomputing, Journal of Elsevier. v73, Issue 1-3, p. 517-524, 2009.

15. M. H. Bahari, H. Fadishei, R. Rajaei, Genetic Fuzzy Maneuvering Target Tracker, International Journal of Factory, Automation, Robotics and Soft Computing, Issue 3, pp. 45-50, 2009.

16. R. Rajaei, B. Vosoughi Vahdat, A GA and PSO-based hybrid algorithm for function approximation, 4^th ACM International Conference on Intelligent Computing and Information Systems (ACM-ICICIS 2009), CAIRO, EGYPT March 19-22, 2009.

17. M. H. Bahari, A. Bahari, F. Nejatimoharrami, R. Rajaei, B. Vosoughi Vahdat, Forecasting the Rate of Penetration Using Bourgoyne and Young Model Associated with Genetic Algorithm, 4^th ACM International Conference on Intelligent Computing and Information Systems (ACM-ICICIS 2009), CAIRO, EGYPT March 19-22, 2009.

18. M. H. Bahari, H. Fadishei, R. Rajaei; Book Chapter: Genetic Fuzzy Maneuvering Target Tracker, Emerging Technologies, Robotics and Control Systems, Third edition, pp. 203-208, 2009. (ISBN: 978-88-901928-8-3)

Technical Referee (selected)

IEEE Transactions on Device and Materials Reliability (TDMR).

Microelectronics Journal (MEJ), Elsevier.

Journal of Circuits, Systems and Computers (JCSC), World Scientific.

Microelectronic Reliability (MR), Elsevier.

Research and Teaching Experience (2008-2015)

Fall 2015-Now:

Assistant Professor, Department of Electrical Engineering, Shahid Beheshti University (SBU).

Spring 2015:

Fundamentals of Electrical Engineering-I (SUT)

Computer Aided Digital System Design (IUST)

Fall 2014: